1. Field of the Invention
The present invention relates to a data processor and, more particularly, to a single chip data processor having an instruction fetch bus and a data bus provided separately from each other for a read only memory (ROM).
2. Description of the Prior Art
In a data processor in which an internal ROM is provided for storing a program consisting of instruction codes and operand data to be processed (called collectively "data"), it is necessary to check whether or not the data stored in the ROM are correct at the time of its manufacture. It is also necessary to ensure the data-read-out paths from the ROM. In particular, in a data processor of the type in which an instruction fetch bus and an internal data bus are provided separately, check of both of the output path to the data bus from the ROM and the output path to the fetch bus from the ROM becomes necessary.
Referring now to FIG. 5, the conventional data processor 500 of such a type is constructed as a three-bus configuration in which an internal data bus 504, an internal instruction fetch bus 506 and an internal address bus 510 are provided separately from one another. This data processor further includes a program counter 501, an internal ROM 502, an external bus 505 coupled to the data bus 504, an instruction decoder 508 coupled to the fetch bus 506, an execution unit (EXU) 509 coupled to the decoder 508 and the data bus 504.
The data processor 500 has three operation modes consisting of a normal operation mode, a test execution mode and a ROM-data read-out mode. In the normal operation mode, the programs stored in a user area of the ROM 502 is executed. In the test execution mode, a test program stored in a test area of the ROM 502 is executed to test the respective circuit operation. In the read-out mode, the data in the ROM 502 is read out to the outside. One of these operation modes is selected by means of a mode switching circuit (not shown).
In checking the contents of the ROM 502, therefore, the ROM-data read-out mode, is selected and initiated to read out the data of the ROM 502 by sequentially supplying addresses thereto from the program counter 501. The data read out of the ROM 502 are then transferred to the internal data bus 504 through the output path 503 and further to the external bus 505. The data transferred to the external bus 505 are compared with the (expected data) by an externally provided testing device. At this time, the output path 503 from the ROM 502 to the internal data bus 504 is checked simultaneously. However, the output path 507 from the ROM 502 to the internal fetch bus 506 is not checked. In order to check the output path 507, therefore, the data processor is next brought into the testing execution mode to execute the test program stored in the test area of the ROM 502. The execution resultant data are compared with the expected values by means of the testing device. In this way, whether the instruction codes of the testing programs are read correctly can be determined together with checking a data transfer path including the output path 507.
Turning to FIG. 6, there is shown another data processor 600 which is disclosed in Japanese Laid-Open Patent Application Sho. 64-15835. This data processor 600 also employs the three-bus configuration consisting of an internal bus 604, an internal fetch bus 606 and an internal address bus 612, and includes a program counter 601, an internal ROM 602, an output path 603, an external bus 605, an output path 607, an instruction decoder 611, and an EXU 613. This EXU 613 is constituted by including a first EXU register 608, a second EXU register 609 and an arithmetic and logic unit (ALU) 610. In this data processor 600, to check the built-in ROM 602 the processor is set to the ROM read mode, so that the data in the ROM 602 are read based on the addresses produced sequentially by the program counter 601 and then transferred to the internal data bus 604 through the output path 603, as shown in the timing charts of FIGS. 7A-7G. However, the data transferred to the internal data bus 604 are latched in the first EXU register 608 within the EXU 613 instead of being output to the external bus 605. The expected values are read from the outside through the external bus 605, and are latched in the second EXU register 609 through the internal data bus 604. Subsequently, the data in the first EXU register 608 and the data in the second EXU register 609 are compared by the ALU 610, and the comparison result is output to the outside through the internal data bus 604 and the external bus 605. The data on the external bus 605 are compared with the expected values by means of an external testing device. Thus, the output path 603 from the built-in ROM 602 to the internal data bus 604 is checked simultaneously. Since the output path 607 from the built-in ROM 602 to the internal fetch bus 606 is not checked, however, the test operation mode is set and initiated similarly to the data processor 500 as shown in FIG. 5.
Specifically, similar to the case of the conventional data processor as shown in FIG. 5, the data processor is next set to the testing executing mode in order to check the output path 607, and the processor executes the testing programs stored for testing in advance in the test area of the built-in ROM 602 in a manner similar to the normal operation mode and the state of an external terminal (not shown) connected to the internal fetch bus 606 during the execution sequence is compared with the expected values by means of an external testing device. In this way, whether the instruction codes of the testing programs are read correctly can be determined, thereby enabling the indirect check on the output path 607.
In the conventional data processors described in the above, the check on the built-in ROM and the check on the output path from the built-in ROM to the internal data bus in the built-in ROM read mode, and the check on the output path from the built-in ROM to the internal fetch bus in the testing execution mode have to be carried out separately, so that there exists a problem in that the reduction in the test-turnaround-time (TAT) is not easy.
Moreover, the check on the output path from the built-in ROM to the internal fetch bus is carried out indirectly by the execution of the instruction codes of the testing programs stored in the test area of the built-in ROM. Therefore, the data that can be passed from the built-in ROM to the internal fetch bus are restricted to the instruction codes of the testing programs stored in the test region of the built-in ROM having only a limited memory space, so that it has a problem in that the bit patterns of the data are restricted and the testability is deteriorated.
Further, it is necessary to place testing programs by securing a test area in the built-in ROM, which results in the reduction in the user area or the increase in the space of the built-in ROM, giving rise to the problem of obstructing the improvement of the cost performance.